An Approach to Formalize UML Sequence Diagrams in CSP

UML sequence diagrams are widely used in mod-eling system behaviors in the early design phases of software development. In order to support formal model verification and refinement, sequence diagrams need to be formalized in a formal language. In this paper, we propose an approach to formalize UML sequence diagrams in CSP (communicating and sequential processes) in order to use FDR, a model checking tool, for system analysis and verification. In the approach, we construct a CSP process for each lifeline of the sequence diagram by extracting messages and combined fragments covered by the lifeline, and sequencing them in time order. A message’s sending or receiving event is converted to a CSP event. Combined fragments are transformed to condition operators or external choices. We define channels for passing messages between two processes. Through parallel composition of processes using events occur in channels as their alphabets, we build the CSP model for the sequence diagram. A tool based on XSLT has been developed to support the approach. KeywordsUML, Formalization, Sequence diagrams, CSP